Made in China: Low-Level Register Programming for Bluetooth Classic SCO Audio on Actions ATS285x Chips

Made in China: Low-Level Register Programming for Bluetooth Classic SCO Audio on Actions ATS285x Chips

In the rapidly evolving landscape of wireless audio, the Actions ATS285x family of Bluetooth audio SoCs (System on Chips) has emerged as a prominent choice for mid-range and high-volume consumer products, particularly in the Chinese manufacturing ecosystem. While high-level APIs and Bluetooth stacks abstract much of the complexity, achieving optimal performance, low latency, and power efficiency for classic Bluetooth SCO (Synchronous Connection-Oriented) audio—the backbone of voice calls and hands-free profiles—often requires diving into low-level register programming. This article explores the technical intricacies of programming SCO audio on the ATS285x at the register level, focusing on the integration with the HCI (Host Controller Interface) transport and the PCM (Pulse Code Modulation) interface.

Understanding the ATS285x Audio Architecture

The ATS285x integrates a Bluetooth baseband core, an ARM Cortex-M series microcontroller, and a dedicated audio subsystem. For classic Bluetooth, the chip handles both BR/EDR (Basic Rate/Enhanced Data Rate) radio and link control. The SCO link is established over the air using a reserved set of time slots, typically carrying 64 kb/s CVSD (Continuously Variable Slope Delta) or A-law/μ-law PCM encoded audio. On the host side, the audio data can be routed through:

• HCI SCO Data: Audio packets are sent via the HCI transport (usually UART or USB) to the host processor for further processing (e.g., noise suppression, echo cancellation).
• PCM Interface: The chip provides a hardware PCM bus that can be directly connected to an external codec or a digital microphone array. This path offers lower latency and offloads the host from real-time audio streaming.

Low-level register programming on the ATS285x typically involves configuring the PCM interface timing, the SCO link parameters, and the data routing between the Bluetooth core and the audio peripherals. The chip’s datasheet and reference manual provide a memory-mapped register set, often accessed through direct writes to addresses like 0x4000_8000 for audio-related blocks.

Configuring the PCM Interface for SCO

The PCM interface on the ATS285x is highly configurable. It supports both short and long frame sync modes, configurable bit clock polarity, and data alignment. To connect an external codec for a hands-free car kit, for example, the following register settings are typical:

// Assume base address of PCM controller is 0x4000_8000
#define PCM_CTRL_REG      (*(volatile uint32_t *)0x4000_8000)
#define PCM_CLK_DIV_REG   (*(volatile uint32_t *)0x4000_8004)
#define PCM_FRAME_CFG_REG (*(volatile uint32_t *)0x4000_8008)

// Enable PCM interface, set to master mode (chip provides clock and frame sync)
// Bit 0: Enable (1)
// Bit 1: Master/Slave (1 = Master)
// Bits 2-3: Frame Sync Width (00 = short frame sync, 01 = long frame sync)
PCM_CTRL_REG = 0x00000003; // Enable, Master, short frame sync

// Set bit clock divider for 8 kHz audio, 16-bit samples, 2 channels (stereo) but SCO is mono
// Required bit clock frequency = 8000 Hz * 16 bits * 2 channels = 256 kHz
// Assuming system clock is 48 MHz: divider = 48000000 / 256000 = 187.5 -> use 187
PCM_CLK_DIV_REG = 187; // Produces ~256.4 kHz (within tolerance)

// Configure frame sync: active low, length 1 bit clock, 8 kHz rate
// Bits 0-7: Frame sync divider (256 kHz / 8000 = 32 bit clocks per frame)
// Bit 8: Frame sync polarity (0 = active low, 1 = active high)
// Bit 9: Frame sync length (0 = 1 bit clock wide, 1 = 1 word wide)
PCM_FRAME_CFG_REG = (32 << 0) | (0 << 8) | (0 << 9);

This configuration establishes a standard PCM bus running at 256 kHz bit clock, with a frame sync pulse every 32 bit clocks (matching an 8 kHz frame rate). The SCO audio from the Bluetooth core, typically 8 kHz 16-bit linear PCM, can be routed to this interface via another set of registers in the audio router block.

Routing SCO Audio to the PCM Interface

The ATS285x provides a crossbar or audio routing matrix that connects the Bluetooth SCO data paths to the PCM interface. This is often controlled by a set of registers in the "Audio Switch" or "SCO Router" module. For example, to route the incoming SCO audio (from the remote peer) to the PCM output, and the PCM input (from the local microphone) to the outgoing SCO stream, the following conceptual register writes might be used:

// Base address for audio router: 0x4000_9000
#define AUDIO_ROUTER_IN_SEL  (*(volatile uint32_t *)0x4000_9000)
#define AUDIO_ROUTER_OUT_SEL (*(volatile uint32_t *)0x4000_9004)

// Route SCO RX (receive) data to PCM output channel 0
// Bits 0-3: Source select (0 = SCO RX, 1 = PCM RX, etc.)
// Bits 4-7: Destination select (0 = PCM TX, 1 = I2S TX, etc.)
AUDIO_ROUTER_IN_SEL = (0x0 << 0) | (0x0 << 4); // SCO RX -> PCM TX

// Route PCM RX (microphone input) to SCO TX (transmit)
AUDIO_ROUTER_OUT_SEL = (0x1 << 0) | (0x1 << 4); // PCM RX -> SCO TX

Note that the exact register bit assignments vary between chip revisions. The above is a simplified example based on common SoC design patterns. In practice, the Actions SDK provides macro definitions for these fields, but a deep understanding of the register map is essential for debugging or optimizing performance.

Performance Analysis and Latency Considerations

One of the primary reasons for low-level register programming is to minimize latency. Bluetooth SCO audio over HCI introduces significant buffering and protocol overhead. By using the direct PCM path, the ATS285x can achieve end-to-end latency as low as 10-15 ms (from microphone ADC to speaker DAC), compared to 40-60 ms when using HCI SCO. However, this requires careful timing synchronization.

The PCM interface must operate synchronously with the Bluetooth baseband's slot timing. The ATS285x typically uses a 312.5 µs Bluetooth slot period. For an 8 kHz SCO link, one audio frame (125 µs) fits into less than half a Bluetooth slot. The register configuration must ensure that the PCM DMA (Direct Memory Access) transfers are triggered at the correct Bluetooth clock edges. This is often handled by a "PCM sync" register that aligns the frame sync with the Bluetooth clock:

// PCM sync register at 0x4000_800C
// Bit 0: Enable sync to Bluetooth clock
// Bits 8-15: Bluetooth clock slot offset (in units of 1/2 slot)
#define PCM_SYNC_REG (*(volatile uint32_t *)0x4000_800C)
PCM_SYNC_REG = (1 << 0) | (0x2 << 8); // Enable sync, start PCM frame 1 slot after BT clock tick

Improper alignment can cause buffer underruns or overruns, leading to audible clicks or pops. During development, monitoring the PCM FIFO status registers (e.g., underflow/overflow flags) is crucial. For example:

#define PCM_STATUS_REG (*(volatile uint32_t *)0x4000_8010)
if (PCM_STATUS_REG & 0x1) {
    // PCM TX underflow occurred - increase DMA buffer size or adjust sync offset
    PCM_STATUS_REG |= 0x1; // Clear flag
}

Protocol Details: SCO Packet Handling

At the Bluetooth protocol level, SCO packets are transmitted using HV (High-quality Voice) packets: HV1, HV2, or HV3, with increasing error correction overhead. The ATS285x baseband handles this automatically, but the host can influence the SCO link configuration via HCI commands. For register-level control, the developer can set the SCO packet type during link establishment by writing to the link manager's control registers. For example, to force HV3 (best bandwidth efficiency) for a voice call:

// HCI register for SCO parameters (conceptual)
#define HCI_SCO_PKT_TYPE_REG (*(volatile uint32_t *)0x4000_2000)
// Bits 0-1: Packet type (0 = HV1, 1 = HV2, 2 = HV3)
HCI_SCO_PKT_TYPE_REG = 0x2; // Select HV3

This low-level control is rarely exposed in high-level SDKs but is critical for tuning power consumption and audio quality. HV3 uses 1.25 ms intervals and provides 64 kb/s data rate, while HV1 uses 3.75 ms intervals but offers more retransmission opportunities for noisy environments.

Conclusion

Low-level register programming for Bluetooth Classic SCO audio on Actions ATS285x chips is a domain where Chinese semiconductor companies have demonstrated significant engineering depth. By directly manipulating the PCM interface timing, audio routing, and SCO link parameters, developers can achieve superior latency and power efficiency compared to relying solely on high-level stacks. The examples provided—PCM clock configuration, audio routing register settings, and sync alignment—illustrate the level of control available to engineers who are willing to work at the hardware abstraction layer.

As Bluetooth technology evolves, with the latest Bluetooth 6.0 specification introducing new features like channel sounding, the fundamental principles of register-level audio path configuration remain relevant. For embedded developers working with Chinese-manufactured SoCs like the ATS285x, mastering these low-level details is not just an academic exercise—it is a practical necessity for building competitive, high-performance wireless audio products.

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